Search results

Do state governments have the ability to predict the onset, duration, and depth of structural fiscal crisis? The State of Indiana had a particularly difficult time recovering from the recession that began in April 2001. Painful expenditure restraint and substantive revenue increases were necessary simply to “break even” from 2002 through 2006. Could early warning signs have permitted more timely actions to avert the subsequent pain? Using monthly cash receipts and balances, we test whether these data hold predictive value in forecasting the onset and severity of fiscal imbalance. The evidence strongly suggests that the structural character of the 2001-02 deficit and its subsequent depth was discernible in the cash receipts stream early enough to take ameliorating action. That the state did not do so reflects budgetary psychology more than the deficit’s predictability.

Do state governments have the ability to predict the onset, duration, and depth of structural fiscal crisis? The State of Indiana had a particularly difficult time recovering from the recession that began in April 2001. Painful expenditure restraint and substantive revenue increases were necessary simply to "break even" from 2002 through 2006. Could early warning signs have permitted more timely actions to avert the subsequent pain? Using monthly cash receipts and balances, we test whether these data hold predictive value in forecasting the onset and severity of fiscal imbalance. The evidence strongly suggests that the structural character of the 2001-02 deficit and its subsequent depth was discernible in the cash receipts stream early enough to take ameliorating action. That the state did not do so reflects budgetary psychology more than the deficit’s predictability.

I. Introduction to the Study of the Economic Role of Government: Alternative Approaches to Law and Economics

X = multiple interpretations

The two sets of notes, taken only three years apart are substantially similar in organization and content. We document differences identified in a line-by-line comparison in Table 1. Generally, the 1996 course notes reproduced here more prominently feature the work of legal scholars, from Oliver Wendell Holmes to St. George Tucker. Curiously, many of these references were removed from the later version, as well as nearly all discussion on legal precedent established by Supreme Court cases. The overall effect of these changes is a marked shift away from a critical legal studies approach to the economic role of government and toward a more focused neoclassical lens.

The purpose of this work is to reduce the power consumption of KSA and to improve the PDP for data path applications. In digital Very Large – Scale Integration systems, the addition of two numbers is one of the essential functions. This arithmetic function is used in the modern digital signal processors and microprocessors. The operating speed of these processors depends on the computation of the arithmetic function. The speed computation block for most of the datapath elements was adders. In this paper, the Kogge–Stone adder (KSA) is designed using XOR, AND and proposed OR gates. The proposed OR gate has less power consumption due to the less number of transistors. In arithmetic logic circuit power, delay and power delay products (PDP) are considered as the important parameters. The delays reported for the proposed OR gate are less when compared with the conventional Complementary Metal Oxide Semiconductor (CMOS) OR gate and pre-existing logic styles. The proposed circuits are optimized in terms of power, delay and PDP. To analyze the performance of KSA, extensive Cadence Virtuoso simulations are used. From the simulation results based on 45 nm CMOS process, it was observed that the proposed design has obtained 688.3 nW of power consumption, 0.81 ns of delay and 0.55 fJ of PDP at 1.1 V.

In this paper, a new circuit for OR gate is proposed. The KSA is designed using XOR, AND and proposed OR gates.

The proposed OR gate has less power consumption due to the less number of transistors. The delays reported for the proposed OR gate are less when compared with the conventional CMOS OR gate and pre-existing logic styles. The proposed circuits are optimized in terms of power, delay and PDP.

In arithmetic logic circuit power, delay and PDP are considered as the important parameters. In this paper, a new circuit for OR gate is proposed. The power consumption of the designed KSA using the proposed OR gate is very less when compared with the conventional KSA. Simulation results show that the performance of the proposed KSA are improved and suitable for high speed applications.